SigmaQuad/DDR IIIe/IVe SRAM Overview

Introduction

GSI’s SigmaQuad and SigmaDDR IIIe and IVe families of synchronous SRAMs have been designed to deliver significantly greater performance than that provided by the older-generation II and II+ families (the highest performance commercially-available synchronous SRAMs prior to the advent of the IIIe family). Both the IIIe and IVe families come in 3 functional variations—Quad B2 (Separate I/O, Burst of 2), Quad B4 (Separate I/O, Burst of 4), and DDR B2 (Common I/O, Burst of 2), and in 2 configurations—x18 and x36.

The Quad B2 device can execute two operations, a Read and a Write, per cycle, whereas the Quad B4 and DDR B2 devices can only execute one operation, a Read or a Write, per cycle. Consequently, at a given operating frequency, the Quad B2 device provides twice the transaction rate of the Quad B4 and DDR B2 devices, with equivalent per-pin data bandwidth. And as transaction rate has become the primary driver of SRAM performance requirements in the Networking & Telecom markets, Quad B2 performance is the primary focus of the IIIe and IVe families.

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GSI ECCRAMs, The Benefits of On-Chip ECC

Introduction
Error Correction Code, or ECC, is commonly utilized with SRAMs in applications where data corruption via SER events is not easily tolerated. Typically, the ECC algorithms detect and correct single-bit data errors. In some instances they can also detect multi-bit errors, depending on the type of algorithm used and the number of parity bits allocated to ECC.

Traditionally, in environments that require high data integrity, the ECC error detection and correction algorithms have been implemented in custom ASIC- and FPGA-based memory controllers. However, it has become increasingly rare for such controllers to be designed in-house, due to cost, resource, and time-to-market constraints. Unfortunately, the availability of 3rd party, off-the-shelf SRAM controllers designed for the commercial market is quite limited, and those that are available often do not support ECC functionality, leaving SER-sensitive SRAM users in a difficult situation.
Bringing the ECC on-chip resolves the issue by removing the burden from the controller, thereby simplifying custom controller design and maximizing 3rd party controller options for the application. It also provides utilization efficiency benefits that are explained further below.
Accordingly, GSI Technology has developed a family of SigmaQuad™ and SigmaDDR™ SRAMs with on-chip ECC, referred to collectively as “ECCRAMs”.

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