GSI’s SigmaQuad and SigmaDDR IIIe and IVe families of synchronous SRAMs have been designed to deliver significantly greater performance than that provided by the older-generation II and II+ families (the highest performance commercially-available synchronous SRAMs prior to the advent of the IIIe family). Both the IIIe and IVe families come in 3 functional variations—Quad B2 (Separate I/O, Burst of 2), Quad B4 (Separate I/O, Burst of 4), and DDR B2 (Common I/O, Burst of 2), and in 2 configurations—x18 and x36.
The Quad B2 device can execute two operations, a Read and a Write, per cycle, whereas the Quad B4 and DDR B2 devices can only execute one operation, a Read or a Write, per cycle. Consequently, at a given operating frequency, the Quad B2 device provides twice the transaction rate of the Quad B4 and DDR B2 devices, with equivalent per-pin data bandwidth. And as transaction rate has become the primary driver of SRAM performance requirements in the Networking & Telecom markets, Quad B2 performance is the primary focus of the IIIe and IVe families.